source ../scripts/dc_setup.tcl

sh mkdir -p ../rpts
sh mkdir -p ../output
sh mkdir -p ../log
sh mkdir ../db

set top soc_top

####new add
set hdlin_shorten_long_module_name true
set hdlin_module_name_limit 255

set_svf ../output/${top}.svf

set_host_options -max_cores 4

define_design_lib temp_work -path ./tmp_work

#full path 

set rtl_top_loc "/team/riscv/rtl" 
set rtl_cpu_core_loc "/team/riscv/rtl/cpu_core" 
set rtl_perips_loc "/team/riscv/rtl/perips" 
set rtl_slot_loc "/team/riscv/rtl/slot" 
set rtl_bus_loc "/team/riscv/rtl/bus_ASIC" 
set rtl_utils_loc "/team/riscv/rtl/utils" 

#set RTL search path
set search_path  [list $rtl_top_loc $rtl_cpu_core_loc $rtl_perips_loc $rtl_slot_loc $rtl_bus_loc $rtl_utils_loc]
#identify list of verilog files to analyze, elaborate
set verilog_file ""
set vfile [open "../input/read_rtl_list.tcl" r]
gets $vfile line
while {$line != ""} {
    regsub -all " " $line "" line
    regsub -all "\t" $line "" line
    set verilog_file "$verilog_file $line"
    gets $vfile line
}
close $vfile

####### Analysis
analyze -format verilog -lib work "${verilog_file}" > ../log/analyze.log

###### Elaboration
elaborate $top -lib work

current_design $top
change_names -rules verilog -hierarchy
check_design > ../rpts/${top}_read.check
link

write -output ../db/${top}.readrtl.ddc -format ddc -hierarchy
write -output ../output/${top}.readrtl.v -format verilog -hierarchy

source -echo -verbose ../input/dont_touch.tcl 
####################### compile ##################
# link and uniquify
set uniquify_naming_style ${top}_%s_%d
current_design $top
uniquify
link

#read sdc file
source -echo -verbose ../input/disable.sdc 

#set_message_info -id OPT-314 -limit 20
#set_message_info -id UCN-1 -limit 20

read_sdc ../input/${top}.sdc
source -echo -verbose ../input/${top}.sdc

#critical path opt scope
set_critical_range 3 [current_design]

####physical cons
#set_ignored_layers -min_routing_layer M1 -max_routing_layer M6
#
#read_floorplan /disk2/course/proj/oc8051/flow/pnr/output_data/v0/init_floorplan.for_dct.tcl
#
#set_clock_gating_style \
        -positive_edge_logic {integrated:saed90nm_max_hth_cg_lvt/CGLPPRX8_LVT} \
        -control_point before \
        -max_fanout 32 \
        -no_sharing \
        -minimum_bitwidth 8 \
        -sequential_cell latch
   
#extra cmds
#set_structure false
#set_flatten true -effort high

#### compile setup
#keep constant register
set_app_var compile_seqmap_propagate_constants false
set_app_var compile_seqmap_propagate_high_effort false
set_app_var case_analysis_with_logic_constants true
##new add
#Rewire in the hierarchy to repair multi-port nets, feedthrough, and constant-driven ports
set_app_var compile_advanced_fix_multiple_port_nets  true
#prevent register merging on all registers in the design
set_app_var compile_enable_register_merging      false
set_app_var access_internal_pins                true
#setup significant digits for reports 
set_app_var report_default_significant_digits  3

#keep unused design
set_app_var ungroup_keep_original_design false
#turn off the automatic ungrouping of small user design hierarchies
set_app_var compile_ultra_ungroup_small_hierarchies false
#do not allow inversion of reg outputs for opt
set_app_var compile_seqmap_enable_output_inversion false
#all clocks that go to a given reg are analyzed with the same weight
set_app_var timing_enable_multiple_clocks_per_reg true

#analyzed RTL is allowed to have PG ports
set_app_var dc_allow_rtl_pg true

#do not tie off unused hierarchical pins
set_app_var bind_unused_hierarchical_pins false
#accept recovery and removal arcs from tech library
set_app_var enable_recovery_removal_arcs "true"

#give verbose informations during elaborate about inferred registers/latches
set_app_var hdlin_check_no_latch true
set_app_var hdlin_reporting_level verbose
#process VHDL configurations if possible
set_app_var hdlin_enable_configurations true
#get proper name derived from generate statements
set_app_var hdlin_enable_hier_naming true

#synthetic DesignWare libraries
set_app_var synlib_wait_for_design_license [list "DesignWare"]
#set_app_var verilogout_no_tri true

#eliminate the assign statement
set_fix_multiple_port_nets -all -buffer_constants
#set_fix_mulitple_port_nets -feedthroughs

set_register_merging [current_design] false
set_ungroup [current_design] false
#set_app_var dont_touch_nets_with_size_only_cells true

#SDC output
set_app_var write_sdc_output_lumped_net_capacitance false
set_app_var write_sdc_output_net_resistance false
#avoid -hsc options in SDC
set_app_var sdc_write_unambiguous_names true
#set_ungroup_keep_original_design true
#compile_ultra -gate_clock -scan -timing_high_effort_script
#compile
compile_ultra -no_autoungroup

set_app_var verilogout_no_tri true

#sdc
#source -echo -verbose ../input/disable.sdc

#report_timing
#report_timing -to */D -delay min

#statistics cells numbers
sizeof_collection [get_cells -hierarchical -filter "is_mapped"] 
#sizeof_collection [get_cells -hierarchical *] 
#report_qor


report_constraint -all_violators  > ../rpts/${top}_all_vios1.rpt
report_constraint -nosp -all_violators > ../rpts/${top}_vio_sum.rpt
report_qor > ../rpts/${top}_qor.rpt
report_power > ../rpts/${top}_power.rpt
report_area > ../rpts/${top}_area.rpt
report_area -hierarchy > ../rpts/${top}_area_hie.rpt
report_timing > "../rpts/${top}_timing.rpt"
#compile_ultra -incr -only_design_rule 
##Ecompile_ultra -incremental -scan -spg
#report_constraint -all_violators  > ../rpts/all_vios2.incr.rpt

set_svf -off

#output data
change_names -rules verilog -hierarchy
write -format ddc -hierarchy -output ../output/${top}.mapped.ddc
write -f verilog -hierarchy -output ../output/${top}.mapped.v

write_sdf ../output/${top}.sdf
write_sdc  ../output/${top}.sdc

puts "INFO: Complete of Compile"


